In recent years, studies are actively made with regard to a ferroelectric-type nonvolatile semiconductor memory having a large capacity. A ferroelectric-type nonvolatile semiconductor memory (to be sometimes abbreviated as “nonvolatile memory” hereinafter) permits rapid access and is nonvolatile, and it consumes less electric power and has strength against an impact, so that it is expected to be used as a main storage device in various electronic machines and equipment having functions of file storage and resume, such as a portable computer, a cellular phone and a game machine, or as a recording medium for recording voices or images.
The above nonvolatile memory is a fast rewritable nonvolatile memory according to a method in which a change in an accumulated charge amount in a capacitor member having a ferroelectric layer is detected by utilizing fast polarization inversion and residual polarization of the ferroelectric layer, and the nonvolatile memory basically comprises the memory cell (capacitor member) and a transistor for selection. The memory cell (capacitor member) comprises, for example, a lower electrode, an upper electrode and the ferroelectric layer interposed between these electrodes. Data is written into and read out from the above nonvolatile memory by using the P-E (V) hysteresis loop of the ferroelectric layer shown in FIG. 60. That is, when an external electric field is applied to the ferroelectric layer and then removed, the ferroelectric layer exhibits residual polarization. When an external electric field in the plus direction is applied, the residual polarization of the ferroelectric layer comes to be +Pr, and when an external electric field in the minus direction is applied, it comes to be −Pr. When the residual polarization is in the state of +Pr (see “D” in FIG. 60), such a state represents “0”, and when the residual polarization is in the state of −Pr (see “A” in FIG. 60), such a state represents “1”.
For discriminating the state of “1” or “0”, an external electric field, for example, in the plus direction is applied to the ferroelectric layer, whereby the polarization of the ferroelectric layer comes into the state of “C” in FIG. 60. In this case, when the data is “0”, the polarization state of the ferroelectric layer changes from the state of “D” to the state of “C”. When the data is “1”, the polarization state of the ferroelectric layer changes from the state of “A” to the state of “C” through the state of “B”. When the data is “0”, the polarization inversion does not take place in the ferroelectric layer. When the date is “1”, the polarization inversion takes place in the ferroelectric layer. As a result, there is caused a difference in the accumulated charge amount in the memory cell (capacitor member). The above accumulated charge is detected as a signal current by bringing, into an ON-state, the transistor for selection in a selected nonvolatile memory. When the external electric field is brought into 0 after data is read out, the polarization state of the ferroelectric layer comes into the state of “D” in FIG. 60 both when the data is “0” and when it is “1”. That is, when the data is read out, the data “1” is once destroyed. When the data is “1”, therefore, the polarization is brought into the state of “A” through “D” and “E” by applying the external electric field in the minus direction, to re-write data “1”.
The structure and the operation of a currently mainstream nonvolatile memory are proposed by S. Sheffiled et al. in U.S. Pat. No. 4,873,664. The above nonvolatile memory comprises two nonvolatile memory cells as shown in a circuit diagram of FIG. 61. In FIG. 61, each nonvolatile memory is surrounded by a dotted line. Each nonvolatile memory comprises, for example, transistors for selection TR11 and TR12 and memory cells (capacitor members) FC11 and FC12.
Concerning two-digit or three-digit subscripts, for example, a subscript “11” is a subscript that should be shown as “1,1”, and for example, a subscript “111” is a subscript that should be shown as “1,1,1”. For simplified showing, the subscripts are shown as two-digit or three-digit subscripts. Further, a subscript “M” is used to show, for example, a plurality of memory cells or plate lines in the block, and a subscript “m” is used to show an individual, for example, of a plurality of the memory cells or the plate lines. A subscript “N” is used to show, for example, transistors for selection or memory units in the block, and a subscript “n” is used to show, for example, an individual of the transistors for selection or the memory units.
Complementary data is written into a pair of the memory cells, and the nonvolatile memory stores 1 bit. In FIG. 61, symbol “WL” stands for a word line, symbol “BL” stands for a bit line, and symbol “PL” stands for a plate line. When one nonvolatile memory is taken, the word line WL1 is connected to a word line decoder/driver WD. The bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, the plate line PL1 is connected to a plate line decoder/driver PD.
When the stored data is read out from the thus-structured nonvolatile memory, the word line WL1 is selected, and further, the plate line PL1 is driven. In this case, the complementary data appears on a pair of the bit lines BL1 and BL2 as voltages (bit line potentials) from a pair of the capacitor members FC11 and FC12 through the transistors for selection TR11 and TR12. The voltages (bit line potentials) on the pair of the bit lines BL1 and BL2 are detected with the sense amplifier SA.
One nonvolatile memory occupies a region surrounded by the word line WL1 and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, the smallest area of one nonvolatile memory is 8F2 when the minimum fabrication dimension is “F”. Therefore, the thus-structured nonvolatile memory has a smallest area of 8F2.
When it is attempted to increase the capacity of the above-structured nonvolatile memories, its realization can only rely on minuteness of fabrication dimension. Constitution of one nonvolatile memory requires two transistors for selection and two memory cells (capacitor members). Further, it is required to arrange the plate lines at the same pitch as that at which the word lines are arranged. It is therefore almost impossible to arrange the nonvolatile memories at the minimum pitch, and in reality, the area that one nonvolatile memory occupies comes to be much greater than 8F2.
Moreover, it is also required to arrange the word line decoders/drivers WD and the plate line decoders/drivers PD at a pitch equal to a pitch at which the nonvolatile memories are arranged. In other words, two decoders/drivers are required for selecting one low-address. It is therefore difficult to layout peripheral circuits, and the area that the peripheral circuits occupy comes to be large.
One means for decreasing an area of a nonvolatile memory is disclosed in JP-A-121032/1997. As FIG. 62 shows a circuit diagram, the nonvolatile memory disclosed in the above Laid-open comprises two nonvolatile memory cells. One nonvolatile memory cell comprises a plurality of memory cells MC1M (for example, M=4) one end of each of which is connected to one end of one transistor for selection TR1 in parallel, and the other nonvolatile memory cell comprises a plurality of memory cells MC2M one end of each of which is connected to one end of one transistor for selection TR2 in parallel. Lower electrodes of a plurality of the memory cells MC1M, MC2M are in common. The common lower electrode will be referred to as “common node CN1, CN2”. The other ends of the transistors for selection TR1 and TR2 are connected to bit lines BL1 and BL2, respectively. The paired bit lines BL1 and BL2 are connected to a sense amplifier SA. Further, an upper electrode of each of the memory cells MC1m, MC2m (m=1, 2 . . . M) is connected to a common plate line PLm, and the plate line PLm is connected to a plate line decoder/driver PD. Further, the word line WL is connected to a word line decoder/driver WD.
Complementary data is stored in a pair of the memory cells MC1m and MC2m (m=1, 2 . . . M). For reading out the data stored, for example, in the memory cells MC1m and MC2m, (wherein m is one of 1, 2, 3 and 4), the word line WL is selected, and the plate line PLm is driven in a state where a voltage of (½)Vcc is applied to the plate lines PLj (m≠j). The above Vcc is, for example, a power source voltage. By the above procedure, the complementary data appears on a pair of the bit lines BL1 and BL2 as voltages (bit line potentials) from a pair of the memory cells MC1m and MC2m through the transistors for selection TR1 and TR2. And, the sense amplifier SA detects the voltages (bit line potentials) on the pair of the bit lines BL1 and BL2.
A pair of the transistors for selection TR1 and TR2 in the paired nonvolatile memory cells occupy a region surrounded by the word lines WL and a pair of the bit lines BL1 and BL2. If the word lines and the bit lines are arranged at a smallest pitch, therefore, a pair of the transistors for selection TR1 and TR2 in the paired nonvolatile memory cells have a minimum area of 8F2. Since, however, a pair of the transistors for selection TR1 and TR2 are shared by M sets of pairs of the memory cells MC1m and MC2m (m=1, 2 . . . M), the number of the transistors for selection TR1 and TR2 per bit can be decreased, and the layout of the word lines WL is moderate, so that the nonvolatile memory can be easily decreased in size. Further, with regard to the peripheral circuits, M bits can be selected with one word line decoder/driver WD and the plate line decoders/drivers PD that are M in number. When the above constitution is employed, therefore, the layout in which the cell area is close to 8F2 can be attained, and a chip size almost equal to a DRAM can be attained.
Meanwhile, it is known that a polarization attenuation phenomenon called relaxation takes place in a ferroelectric thin film. This phenomenon is a phenomenon in which the ferroelectric thin film is caused to have a constant attenuation in the polarization amount for about 1 second after polarization inversion, and then the polarization is stabilized. It is said that the above polarization attenuation phenomenon is caused because charges trapped inside the ferroelectric thin film are re-distributed depending upon a polarization state. A nonvolatile memory is accessed generally with tens nanoseconds as a unit. After data is written into a memory cell and a transistor for selection is brought into an OFF-state, therefore, the polarization attenuation phenomenon proceeds.
FIGS. 63A and 63B schematically show charge distributions caused by the polarization attenuation phenomenon, in which one memory cell and one transistor for selection are shown for the sake of simplification. FIG. 63A shows a charge distribution when, after a positive-potential pulse is applied to a lower electrode through the transistor for selection in a state where a plate line is grounded, to write data “1”, the lower electrode is again grounded. At a time after completion of data writing, both the lower electrode and the upper electrode are grounded, so that they have the same potentials and charges equivalent to a polarization amount are distributed on each electrode surface, so that an electric field caused by the polarization is cancelled out or offset.
In this case, when the transistor for selection TR is brought to an OFF-state, the lower electrode comes into a floating state. At this time, the polarization of the ferroelectric layer is attenuated as shown in FIG. 63B, but the total charge amount of the lower electrode in a floating state is maintained, so that the potential thereof changes.
A potential change ΔV in the lower electrode after the polarization attenuation phenomenon takes place is as shown by the following expression (1), in which P0 is an initial polarization amount, P1 is a polarization amount after the attenuation, Q is a total charge amount of the lower electrode and CS is a capacity of the memory cell. When the expression (1) is modified, ΔV shown by the expression (2) can be obtained.Q=P0=P1+ΔV·CS  (1)ΔV=(P0−P1)/CS  (2)
When data “1” has been written, ΔV comes to have a positive value, and the potential of the lower electrode increases during storing of the data. When data “0” has been written, ΔV comes to have a negative value, and the potential of the lower electrode decreases during storing of the data. FIG. 63C schematically shows a change in the lower electrode when data “1” is written. First, the potential of the lower electrode increases due to the polarization attenuation phenomenon. After the passage of about 1 second, attenuation of the polarization due to relaxation is saturated, and then, the potential of the lower electrode starts to gradually decrease due to a leak of the ferroelectric layer or a junction. Upon reaching the ground level, the potential of the lower electrode is stabilized.
The above change in the potential of the lower electrode does not cause any problem as far as a nonvolatile memory composed of one memory cell (capacitor member) and one transistor for selection is concerned, since the change does not tend to deteriorate the written data. In a nonvolatile memory disclosed in JP-A-121032/1997, however, the above change poses a big problem.
That is, when it is assumed, for example, that one common node is shared by 16 memory cells, that 15 memory cells among them have data “1” written therein and the remaining one memory cell has data “0” written therein, the common node is greatly affected by the 15 memory cells having data “1” written therein, and as a result, the potential of the common node increases. As a result, an electric field is exerted on the memory cell having data “0” written therein so as to deteriorate the data keeping. Further, the above electric field is maintained until it is attenuated by the leak of the ferroelectric layer or the junction. Therefore, the electric field that tends to deteriorate the data keeping is exerted on the memory cell having data “0” written therein over a long period of time, a length of several seconds, and in a worst case, data destruction occurs in the memory cell having data “0” written therein.
It is therefore an object of the present invention to provide a ferroelectric-type nonvolatile semiconductor memory which is free from destruction of data stored in a memory cell even when a polarization attenuation phenomenon called relaxation takes place in a ferroelectric layer.